Remote opportunity at
IntelliProASIC & FPGA Design Engineer
IntelliPro is hiring a Sr. ASIC and FPGA Design Engineer on a contract listed for 10/12/2026 through 06/30/2027. The role is 100% remote, and the posting…
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About This Role
IntelliPro is hiring a Sr. ASIC and FPGA Design Engineer on a contract listed for 10/12/2026 through 06/30/2027. The role is 100% remote, and the posting pays $100 to $110 per hour on a W2 basis. If the position is later converted to full time, the posting says the engineer would need to relocate to a client location in Southern California or Austin, Texas. The job centers on designing digital…
Job Description
IntelliPro is hiring a Sr. ASIC and FPGA Design Engineer on a contract listed for 10/12/2026 through 06/30/2027. The role is 100% remote, and the posting pays $100 to $110 per hour on a W2 basis. If the position is later converted to full time, the posting says the engineer would need to relocate to a client location in Southern California or Austin, Texas.
The job centers on designing digital and mixed-signal ASICs and FPGAs. The engineer implements designs in VHDL, Verilog or SystemVerilog, builds verification environments and test benches, and writes test plans with coverage models. Sign-off work includes timing and noise analysis, and lab integration and troubleshooting are also part of the role.
The design team partners with systems engineers, firmware developers, architects and product staff. The posting suits an experienced silicon designer with seven or more years of ASIC work, a technical bachelor's degree and hands-on Linux development experience. Advanced degrees, communications and signal-processing knowledge, scripting skills, physical design familiarity and mentoring experience are listed as preferred.
Much of the work involves resolving timing and congestion problems during implementation, so candidates should be comfortable moving from block-level verification to system-level results. The posting does not describe benefits.
Responsibilities
- Design and develop digital ASICs, FPGAs and mixed-signal ASICs
- Implement designs in VHDL, Verilog and SystemVerilog
- Build verification methods, test benches and test harnesses for block and system-level checks
- Write and execute test plans and define coverage models
- Carry out timing and noise analysis plus other sign-off verification
- Work with systems, firmware, architecture and product engineers
- Support lab integration and troubleshooting
- Resolve timing, congestion and other implementation problems
Requirements
- Seven or more years building ASICs, from design through implementation
- Technical bachelor's degree in electrical or computer engineering, or a closely related field
- Experience with both FPGA and ASIC design
- Proficiency in HDL programming with VHDL, Verilog and/or SystemVerilog
- Experience in a Linux development environment
- Hands-on verification work and building test benches
- Strong communication skills and the ability to manage stakeholders
Qualifications
- Advanced degree (MS or PhD) in a related engineering field
- Experience across the full ASIC or FPGA lifecycle, from architecture through integration and test
- Software-defined radio architecture knowledge, plus familiarity with ADCs, DACs and DSPs
- Comms and signal-processing know-how: FEC, spread-spectrum techniques, and QPSK, QAM, PCM/FM or PAM modulation
- Object-oriented programming and scripting in Python, TCL or Perl
- Physical design experience with commercial EDA toolchains, RTL-to-GDSII and sign-off flows
- Familiar with FinFET and CMOS processes at deep sub-micron nodes
- DFT, scan, MBIST and LBIST methodology experience
- Experience mentoring junior engineers
Core Skills
Frequently Asked Questions
Answers are based only on the employer’s listing; where it doesn’t say, neither do we.
Is the position remote?
Yes, the posting lists it as 100% remote. It notes that a full-time conversion would require relocating to a client location in Southern California or Austin, Texas.
What is the pay rate?
The posting lists $100 to $110 per hour on a W2 basis.
When does the contract run?
The posting lists the contract as running from 10/12/2026 through 06/30/2027, in the date format used in the listing.
What experience is needed?
The posting asks for at least seven years in ASIC design and implementation, a bachelor's degree in an electrical, computer engineering or related technical field, and HDL skills.
Sample Interview Questions
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